(1) Field of the Invention
This invention relates to a global bit switch circuit and method for activating a bit switch across a number of sense amplifier sections in more than one bank of sense amplifiers which avoids disruption of non selected sense amplifiers.
(2) Description of the Related Art
U.S Pat. No. 5,923,605 to Mueller et al. describes a multi-bank DRAM capable of overlapped reading and writing to different banks of the DRAM.
U.S. Pat. No. 5,812,473 to Tsai describes a DRAM having a sense amplifier connected to a bit line pair of a memory cell array through a column select switch. The data line pairs are provided with pass gates. A first pair of gates connects a sense amplifier output of a bit line pair to a first data line pair and a second pair of gates connects the sense amplifier output of the bit line pair to a second data line pair. Each bit line pair can be connected through a sense amplifier to either first or second data line pairs.
U.S. Pat. No. 5,949,732 to Kirihata describes a method for structuring a multi-bank DRAM into a hierarchical column select line architecture. The DRAM has multiple banks with a switch for selecting one of the banks and a switch for selecting one of the columns within the bank. This allows switches to couple one of the bit lines to one of the data lines, enabling data to be written into or read out of memory cells common to the selected bank and to the selected column.